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 NTD4858N Power MOSFET
25 V, 73 A, Single N-Channel, DPAK/IPAK
Features
* * * * *
Trench Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb-Free Devices
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V(BR)DSS 25 V
RDS(ON) MAX 6.2 mW @ 10 V
ID MAX 73 A
Applications
* VCORE Applications * DC-DC Converters * High/Low Side Switching
MAXIMUM RATINGS (TJ = 25C unless otherwise stated)
Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJC (Note 1) Power Dissipation RqJC (Note 1) Pulsed Drain Current tp=10ms Steady State TA = 25C TA = 85C TA = 25C TA = 25C TA = 85C TA = 25C TC = 25C TC = 85C TC = 25C TA = 25C TA = 25C PD IDM IDmaxPkg TJ, TSTG IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 25 20 14 10.9 2.0 11.2 8.7 1.3 73 56 54.5 146 45 -55 to +175 45 6 112.5 W A A C A V/ns mJ 4 Drain YWW 48 58NG W A CASE 369AA DPAK (Bent Lead) STYLE 2 W A 12 3 4 Unit V V A G
9.3 mW @ 4.5 V D
S N-CHANNEL MOSFET 4 4
1
2 3 CASE 369AC CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK)
23
1
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain YWW 48 58NG 4 Drain YWW 48 58NG
Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt
Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, VDD = 50 V, VGS = 10 V, IL = 15 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8" from case for 10 s)
TL
260
C
2 1 23 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4858N G = Year = Work Week = Device Code = Pb-Free Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 0
Publication Order Number: NTD4858N/D
NTD4858N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Junction-to-Case (Drain) Junction-to-TAB (Drain) Junction-to-Ambient - Steady State (Note 1) Junction-to-Ambient - Steady State (Note 2) 1. Surface-mounted on FR4 board using 1 sq-in pad, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJC-TAB RqJA RqJA Value 2.75 3.5 73.5 116 Unit C/W
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/ TJ IDSS VGS = 0 V, VDS = 20 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 25 22 1.0 10 100 V mV/C mA nA Symbol Test Condition Min Typ Max Unit
Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH) VGS(TH)/TJ RDS(on)
VGS = VDS, ID = 250 mA
1.45 5.3
2.5
V mV/C
VGS = 10 V VGS = 4.5 V
ID = 30 A ID = 30 A
5.2 7.3 55
6.2 9.3 mW S
Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time
gFS
VDS = 1.5 V, ID = 15 A
CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A VGS = 0 V, f = 1.0 MHz, VDS = 12 V
1563 405 200 12.8 1.3 4.7 5.2 25.7 nC nC 19.2 pF
td(ON) tr td(OFF) tf td(ON) tr td(OFF) tf VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W
12.6 20.2 16.4 5.1 7.7 17.3 23.8 2.8 ns ns
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures.
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NTD4858N
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.87 0.73 11.6 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 7.8 3.7 3.0 nC ns 1.2 V Symbol Test Condition Min Typ Max Unit
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance, DPAK Drain Inductance, IPAK Gate Inductance Gate Resistance
tRR ta tb QRR
LS LD LD LG RG TA = 25C
2.49 0.0164 1.88 3.46 0.7
nH
W
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures.
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NTD4858N
TYPICAL PERFORMANCE CURVES
90 10 V ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 0 1 2 3 4 3.0 V 2.8 V 5 3.4 V 3.2 V 4V 3.6 V 3.8 V TJ = 25C ID, DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 1 TJ = 125C TJ = 25C TJ = -55C 2 3 4 5 VDS 10 V
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 2 3 4 5 6 7 8 9 10 11 ID = 30 A TJ = 25C
0.010 0.009 0.008 0.007 0.006 VGS = 11.5 V 0.005 0.004 0.003 0.002 10 20 30 40 50 60 70 80 90 TJ = 25C VGS = 4.5 V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-to-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) 10000
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V 1000 TJ = 150C TJ = 125C
100
10
1
TJ = 25C
-25
0
25
50
75
100
125
150
175
0.1
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current vs. Drain Voltage
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NTD4858N
TYPICAL PERFORMANCE CURVES
2000 1800 C, CAPACITANCE (pF) 1600 1400 1200 1000 800 600 400 200 0 0 Crss 2.5 5 7.5 10 12.5 15 17.5 20 Coss Ciss VGS = 0 V TJ = 25C 10 QT 8
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS)
6 Q1 Q2
VGS
4
2
0 0
ID = 30 A VDD = 15 V TJ = 25C 4 8 12 16 20 24 28 QG, TOTAL GATE CHARGE (nC)
DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge
30 IS, SOURCE CURRENT (AMPS)
1000 VDD = 15 V ID = 30 A VGS = 11.5 V t, TIME (ns) 100
VGS = 0 V 25 20 15 10 5 0 0.5 TJ = 25C
td(off) tf tr
10
td(on)
1 1
10 RG, GATE RESISTANCE (OHMS)
100
0.6
0.7
0.8
0.9
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) 120
Figure 10. Diode Forward Voltage vs. Current
ID = 15 A 100 80 60 40 20 0 25
100
10 ms 100 ms
10 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 ms 10 ms dc
1
0.1 0.1
50
75
100
125
150
175
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
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NTD4858N
TYPICAL PERFORMANCE CURVES
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.0 D = 0.5
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (ms) P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
0.01 1.0E-05
1.0E-04
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
ORDERING INFORMATION
Device NTD4858NT4G NTD4858N-1G NTD4858N-35G Package DPAK (Pb-Free) IPAK (Pb-Free) IPAK Trimmed Lead (3.5 " 0.15 mm) (Pb-Free) Shipping 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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6
NTD4858N
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE) CASE 369AA-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 --0.035 0.050 0.155 --MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 --0.89 1.27 3.93 ---
-TB V R
4
SEATING PLANE
C E
A S
1 2 3
Z H U
F L D
2 PL
J
DIM A B C D E F H J L R S U V Z
0.13 (0.005)
M
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 3.0 0.118
2.58 0.101
5.80 0.228
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTD4858N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD CASE 369AC-01 ISSUE O
NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25
B V R
C E
A
SEATING PLANE
W F G
K J H D
3 PL
0.13 (0.005) W
DIM A B C D E F G H J K R V W
IPAK (STRAIGHT LEAD DPAK) CASE 369D-01 ISSUE B
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -TSEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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8
NTD4858N/D


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